In mixed-mode CMOS VLSI integrated circuit design, data sampling has been used in many applications, for example, for waveform synthesis, data acquisition, and high speed digital/analog conversion. In applications that deliver a high frequency output signal, a high frequency sampling clock is required and a delay line circuit is often used to provide the high frequency sampling clock. An ordinary integrated delay line circuit is sensitive to variations in power supply changes, temperature changes and process variation, therefore, a more precise delay line technology is needed to compensate for those effects.
Prior art methods of delivering timing pulses with delay are described in U.S. Pat. No. 4,496,861 entitled "Integrated Circuit Synchronous Delay Line", U.S. Pat. No. 4,975,605 entitled "Synchronous Delay Line With Automatic Reset", and in an article entitled "A Novel Precision MOS Synchronous Delay Line", IEEE Journal of Solid State Circuits, Volume SC-20, pp. 1265-1271, December 1985.
Though the above prior art provides timing pulse delay with negative feedback to reduce sensitivity to variations, the output from each delay tap is not a true synchronous delay of the incoming clock signal. In many applications, a more precise timing delay of the incoming reference clock signal is required to provide an accurate data. Although an automatic reset circuit utilized with a delay line circuit has been disclosed in the prior art, the delay line circuit requires sensing circuitry to determine whether or not the delay line circuit is operating in a fundamental mode.
What is needed is an improved precise synchronous delay line circuit is needed to resolve this and other problems associated with conventional delay line circuits. The precise delay line circuit should be easily implemented in existing technologies. It should be cost effective and easily adapted to existing product. Finally, the delay line circuit should eliminate the need for the sense circuitry required in conventional delay line circuits.